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Functional Verification of Heterogeneous Multicore Architectures

Functional verification is widely acknowledged as a major bottleneck in System-on-Chip (SOC) design methodology -- up to 70% of the overall design time and resources are spent on functional verification. In spite of such extensive efforts, majority of the SOC designs fail at the very first time (silicon failures) primarily due to the functional errors. The functional verification complexity is expected to increase further due to the combined effects of increasing design complexity and recent paradigm shift from single processor SOC designs to heterogeneous multicore SOC (HMSOC) architectures. A significant bottleneck in the verification of HMSOC architectures is the lack of a golden reference model and associated design automation techniques. The goal of this research is to develop automated tools and techniques to drastically reduce the functional verification effort as well as to improve the quality of HMSOC architectures. This research will develop innovative techniques for verifying the specification to ensure it can be used as a golden reference model. Furthermore, the golden specification will be used to enable various design automation activities including development of a functional coverage metric, generation of required executable models, and validation of implementation using a combination of simulation-based techniques and formal methods. A successful implementation of this research will have a significant impact in industry as well as in academic research to explore innovative ways of combining top-down and bottom-up approaches for functional verification of future heterogeneous multicore architectures.

	Faculty (PI)		Graduate Students		Undergraduate Students		Collaborators
			Xiaoke Qin		Cris Rivero (REU)		Dhrubajyoti Kalita (Intel)
	Prof. Prabhat Mishra		Mingsong Chen		Cumpase Lawrence III (REU)		Priyadarshan Patra (Intel)
			Kanad Basu		Leon Rogers (REU)
			Sudhi Proch		David Weinberg
			Hadi Hajimiri

Journal Articles:

J5	Kanad Basu and Prabhat Mishra, Test Data Compression using Efficient Bitmask and Dictionary Selection Methods, Accepted to appear in IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI), 2009.
J4	Xiaoke Qin and Prabhat Mishra, A Universal Placement Technique of Compressed Instructions for Efficient Parallel Decompression, Accepted to appear in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 2009.
J3	Heon-Mo Koo and Prabhat Mishra, Functional Test Generation using Design and Property Decomposition Techniques, Accepted to appear in ACM Transactions on Embedded Computing Systems (TECS), volume 8, no 4, pages , 2009.
J2	Seok-Won Seong and Prabhat Mishra, Bitmask-Based Code Compression for Embedded Systems, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), volume 27, no 4, pages 673-685, April 2008.
J1	Mehrdad Reshadi, Prabhat Mishra, and Nikil Dutt, Hybrid Compiled Simulation: An Efficient Technique for Instruction-Set Architecture Simulation, Accepted to appear in ACM Transactions on Embedded Computing Systems (TECS), volume 8, no 3, 27 pages, Article 20, April 2009.

Referred Conference Papers:

C8	Nga Dang, Abhik Roychoudhury, Tulika Mitra and Prabhat Mishra, Generating Test Programs to Cover Pipeline Interactions, Accepted to appear in ACM/IEEE Design Automation Conference (DAC), pages -, San Francisco, California, USA, July 26-31, 2009. Nominated for Best Paper Award
C7	Chetan Murthy and Prabhat Mishra, Lossless Compression using Efficient Encoding of Bitmasks, Accepted to appear in IEEE International Symposium on VLSI (ISVLSI), pages -, Tampa, Florida, USA, May 13-15, 2009.
C6	Chetan Murthy and Prabhat Mishra, Bitmask-based Control Word Compression for NISC Architectures, Accepted to appear in ACM Great Lakes Symposium on VLSI (GLSVLSI), pages -, Boston, USA, May 10-12, 2009.
C5	Xiaoke Qin and Prabhat Mishra, Efficient Placement of Compressed Code for Parallel Decompression, International Conference on VLSI Design, pages 335-340, New Delhi, India, January 5-9, 2009.
C4	Prabhat Mishra and Mingsong Chen, Efficient Techniques for Directed Test Generation using Incremental Satisfiability, International Conference on VLSI Design, pages 65-70, New Delhi, India, January 5-9, 2009. Nominated for Best Paper Award
C3	Heon-Mo Koo and Prabhat Mishra, Specification-based Compaction of Directed Tests for Functional Validation of Pipelined Processors, International Symposium on Hardware/Software Codesign and System Synthesis (CODES+ISSS), pages 137-142, Atlanta, USA, October 19 - 24, 2008.
C2	Kanad Basu and Prabhat Mishra, A Novel Test-Data Compression Technique using Application-Aware Bitmask and Dictionary Selection Methods, ACM Great Lakes Symposium on VLSI (GLSVLSI), pages 83-88, Orlando, USA, May 4 - 6, 2008.
C1	Mingsong Chen, Prabhat Mishra and Dhrubajyoti Kalita, Coverage-driven Automatic Test Generation for UML Activity Diagrams, ACM Great Lakes Symposium on VLSI (GLSVLSI), pages 139-142, Orlando, USA, May 4 - 6, 2008.

• ARTEST: A Prototype Tool for TLM-to-RTL Test Generation: Our tool is a framework that can automatically generate both TLM testcase and RTL testcase from the input SystemC TLM specification. The tool has tree parts: i) TLM2SMV translator, ii) TLM test generator, and iii) RTL test translator from TLM tests. Read more and download ...

This project is funded by the National Science Foundation (NSF). The views expressed on the site are those of the members of this project and do not necessarily represent those of the National Science Foundation.

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