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Upcoming Conferences

Books

B5 Prabhat Mishra, Swarup Bhunia and Mark Tehranipoor (Editors), Hardware IP Security and Trust, ISBN: 978-3-319-49024-3, Springer, 2017.
B4 Mingsong Chen, Xiaoke Qin, Heon-Mo Koo and Prabhat Mishra, System-Level Validation: High-Level Modeling and Directed Test Generation Techniques, ISBN: 978-1-4614-1358-5, Springer, August 2012.
B3 Weixun Wang, Prabhat Mishra and Sanjay Ranka, Dynamic Reconfiguration in Real-Time Systems - Energy, Performance, Reliability and Thermal Perspectives, ISBN: 978-1-4614-0277-0, Springer, July 2012.
B2 Prabhat Mishra and Nikil Dutt (Editors), Processor Description Languages - Applications and Methodologies, Morgan Kaufmann, ISBN: 978-0-12-374287-2, June 2008.
B1 Prabhat Mishra and Nikil Dutt, Functional Verification of Programmable Embedded Architectures - A Top-Down Approach, Springer, ISBN: 0-387-26143-5, July 2005.

Ph.D. Dissertations

D8 Yuanwen Huang, System-on-Chip Vulnerability Analysis and Mitigation Techniques, Ph.D. Dissertation, University of Florida, June 2017.
D7 Kamran Rahmani, Scalable Signal Selection for Post-Silicon Debug, Ph.D. Dissertation, University of Florida, April 2017.
D6 Kanad Basu, Efficient Observability Enhancement Techniques for Post-Silicon Validation and Debug, Ph.D. Dissertation, University of Florida, August 2012.
D5 Xiaoke Qin, System-Level Validation of Multicore Architectures, Ph.D. Dissertation, University of Florida, April 2012.
D4 Weixun Wang, Energy-Aware Scheduling and Dynamic Reconfiguration in Real-Time Embedded Systems, Ph.D. Dissertation, University of Florida, August 2011.
D3 Mingsong Chen, Efficient Approaches for Functional Validation of SoC Designs using High-Level Specifications, Ph.D. Dissertation, University of Florida, August 2010.
D2 Heon-Mo Koo, Coverage-driven Test Generation for Functional Validation of Pipelined Processors, Ph.D. Dissertation, University of Florida, December 2008.
D1 Prabhat Mishra, Specification-driven Validation of Programmable Embedded Systems, Ph.D. Dissertation, University of California, Irvine, March 2004. EDAA Outstanding Dissertation Award 2004.

M.S. Theses

T6 Sudhi Proch, Directed Test Generation for Hybrid Systems, MS Thesis, University of Florida, May 2014.
T5 Prateek Thakyal, Layout-aware Signal Selection for Post-Silicon Debug, MS Thesis, University of Florida, May 2014.
T4 Kartik Shrivastava, Synergistic Integration of Code Compression and Encryption in Embedded Systems, MS Thesis, University of Florida, August 2010.
T3 Chetan Murthy, Decoding-Aware Compression Techniques for Reconfigurable Systems, MS Thesis, University of Florida, December 2008.
T2 Seok-Won Seong, Dictionary-based Code Compression Techniques using Bitmasks for Embedded Systems, MS Thesis, University of Florida, April 2006.
T1 Prabhat Mishra, Illumination Modeling with Reflections, M.Tech. Thesis, Indian Institute of Technology, Kharagpur, January 1996.

Journal Articles

J37 Xiaolong Guo, Raj Gautam Dutta, Prabhat Mishra and Yier Jin, Automatic Code Converter Enhanced PCH Framework for SoC Trust Verification, IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI), 2017.
J36 Ujjwal Gupta, Chetal Patil, Ganapati Bhat, Prabhat Mishra and Umit Ogras, DyPO: Dynamic Pareto Optimal Configuration Selection for Heterogeneous MpSoCs, ACM Transactions on Embedded Computing Systems (TECS), ESWEEK Special Issue, October 2017.
J35 Kamran Rahmani, Sandip Ray and Prabhat Mishra, Post-silicon Trace Signal Selection Using Machine Learning Techniques, IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI), 25(2), pages 570-580, February 2017.
J34 Prabhat Mishra, Ronny Morad, Avi Ziv and Sandip Ray, Post-silicon Validation in the SoC Era: A Tutorial Introduction, IEEE Design & Test (D&T), 34(3), pages 1-25, June 2017.
J33 Yuanwen Huang and Prabhat Mishra, Trace Buffer Attack on the AES Cipher, Springer Journal of Hardware and Systems Security (HASS), 1(1), pages 68-84, 2017.
J32 Mingsong Chen, Xinqian Zhang, Geguang Pu, Xin Fu and Prabhat Mishra, Efficient Resource Constrained Scheduling using Parallel Structure-Aware Pruning Techniques, IEEE Transactions on Computers (TC), 65(7), pages 2059-2073, July 2016.
J31 Kamran Rahmani, Sudhi Proch and Prabhat Mishra, Efficient Selection of Trace and Scan Signals for Post-Silicon Debug, IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI), 24(1), 313-323, 2016.
J30 Mingsong Chen, Xiaoke Qin and Prabhat Mishra, Learning-Oriented Property Decomposition for Automated Generation of Directed Tests, Springer Journal of Electronic Testing (JETTA), 30(3), pages 287-306, 2014.
J29 Kanad Basu and Prabhat Mishra, Restoration-Aware Trace Signal Selection for Post Silicon Validation, IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI), 21(4), pages 605-613, April 2013.
J28 Xiaoke Qin, Weixun Wang and Prabhat Mishra, TCEC: Temperature- and Energy-Constrained Scheduling in Real-Time Multitasking Systems, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 31(8), pages 1159-1168, August 2012.
J27 Weixun Wang, Sanjay Ranka and Prabhat Mishra, Energy-Aware Dynamic Slack Allocation for Real-Time Multitasking Systems, Elsevier Sustainable Computing: Informatics and Systems (SUSCOM), 2(3), pages 128-137, September 2012.
J26 Kanad Basu, Chetan Murthy and Prabhat Mishra, Bitmask aware Compression of NISC Control Words, Elsevier Integration, the VLSI Journal (INTEGRATION), 46(2), pages 131-41, March 2012.
J25 Xiaoke Qin and Prabhat Mishra, Directed Test Generation for Validation of Multicore Architectures, ACM Transactions on Design Automation of Electronic Systems (TODAES), volume 17, no 3, article 24, 21 pages, June 2012.
J24 Hadi Hajimiri, Kamran Rahmani and Prabhat Mishra, Compression-Aware Dynamic Cache Reconfiguration for Embedded Systems, Elsevier Sustainable Computing: Informatics and Systems (SUSCOM), volume 2, issue 2, pages 71-80, June 2012.
J23 Weixun Wang, Prabhat Mishra and Ann-Gordon Ross, Dynamic Cache Reconfiguration for Soft Real-Time Systems, ACM Transactions on Embedded Computing Systems (TECS), volume 11, issue 2, article 28, 31 pages, July 2012.
J22 Mingsong Chen, Prabhat Mishra and Dhrubajyoti Kalita, Automatic RTL Test Generation from SystemC TLM Specifications, ACM Transactions on Embedded Computing Systems (TECS), 11(2), article 38, July 2012.
J21 Mingsong Chen and Prabhat Mishra, Property Learning Techniques for Efficient Generation of Directed Tests, IEEE Transactions on Computers (TC), 60(6), pages 852-864, June 2011.
J20 Weixun Wang and Prabhat Mishra, System-Wide Leakage-Aware Energy Minimization using Dynamic Voltage Scaling and Cache Reconfiguration in Multitasking Systems, IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI), volume 20, issue 5, pages 902 - 910, May 2012.
J19 Weixun Wang and Prabhat Mishra, Dynamic Reconfiguration of Two-Level Cache Hierarchy in Real-Time Embedded Systems, Journal of Low Power Electronics (JOLPE), 7(1), pages 17-28, February 2011.
J18 Weixun Wang, Sanjay Ranka and Prabhat Mishra, Energy-Aware Dynamic Reconfiguration Algorithms for Real-Time Multitasking Systems, Elsevier Sustainable Computing: Informatics and Systems (SUSCOM), 1(1), pages 35-45, March 2011.
J17 Mingsong Chen, Prabhat Mishra and Dhrubajyoti Kalita, Efficient Test Case Generation for Validation of UML Activity Diagrams, Springer Design Automation for Embedded Systems (DAES), 14(2), pages 105-130, 2010.
J16 Xiaoke Qin, Chetan Murthy and Prabhat Mishra, Decoding-aware Compression of FPGA Bitstreams, IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI), 19(3), pages 411-419, March 2011.
J15 Mingsong Chen and Prabhat Mishra, Functional Test Generation using Efficient Property Clustering and Learning Techniques, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 29(3), 396-404, 2010.
J14 Kanad Basu and Prabhat Mishra, Test Data Compression using Efficient Bitmask and Dictionary Selection Methods, IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI), volume 18, issue 9, pages 1277-1286, 2010.
J13 Xiaoke Qin and Prabhat Mishra, A Universal Placement Technique of Compressed Instructions for Efficient Parallel Decompression, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), volume 28, no 8, pages 1224-1236, August 2009.
J12 Heon-Mo Koo and Prabhat Mishra, Functional Test Generation using Design and Property Decomposition Techniques, ACM Transactions on Embedded Computing Systems (TECS), volume 8, no 4, article 32, July 2009.
J11 Seok-Won Seong and Prabhat Mishra, Bitmask-Based Code Compression for Embedded Systems, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), volume 27, no 4, pages 673-685, April 2008.
J10 Mehrdad Reshadi, Prabhat Mishra, and Nikil Dutt, Hybrid Compiled Simulation: An Efficient Technique for Instruction-Set Architecture Simulation, ACM Transactions on Embedded Computing Systems (TECS), volume 8, no 3, 27 pages, Article 20, April 2009.
J9 Prabhat Mishra and Nikil Dutt, Specification-driven Directed Test Generation for Validation of Pipelined Processors, ACM Transactions on Design Automation of Electronic Systems (TODAES), volume 13, no 2, 36 pages, article 42, July 2008.
J8 Prabhat Mishra, Aviral Shrivastava, and Nikil Dutt, Architecture Description Language (ADL)-driven Software Toolkit generation for Architectural Exploration of Programmable SOCs, ACM Transactions on Design Automation of Electronic Systems (TODAES), volume 11, no 3, pages 626-658, July 2006.
J7 Mehrdad Reshadi, Prabhat Mishra and Nikil Dutt, A Retargetable Framework for Instruction-Set Architecture Simulation, ACM Transactions on Embedded Computing Systems (TECS), volume 5, no 2, pages 431-452, May 2006.
J6 Prabhat Mishra, Nikil Dutt, Narayanan Krishnamurthy, and Magdy Abadir, A Methodology for Validation of Microprocessors using Symbolic Simulation, Inderscience International Journal of Embedded Systems (IJES), volume 1, no 1/2, pages 14-22, 2005.
J5 Prabhat Mishra and Nikil Dutt, Architecture Description Languages for Programmable Embedded Systems, IEE Proceedings on Computers and Digital Techniques (CDT), Special issue on Embedded Microelectronic Systems: Status and Trends, volume 152, no 3, pages 285--297, May 2005.
J4 Prabhat Mishra, Mahesh Mamidipaka and Nikil Dutt, Processor-Memory Co-Exploration using an Architecture Description Language, ACM Transactions on Embedded Computing Systems (TECS), volume 3, number 1, pages 140-162, February 2004.
J3 Prabhat Mishra, Nikil Dutt, Narayanan Krishnamurthy, and Magdy Abadir, A Top-Down Methodology for Validation of Microprocessors, IEEE Design and Test of Computers (Design&Test), Special Issue on Functional Verification and Testbench Generation, volume 21, number 2, pages 122-131, 2004.
J2 Prabhat Mishra and Nikil Dutt, Modeling and Validation of Pipeline Specifications, ACM Transactions on Embedded Computing Systems (TECS), volume 3, number 1, pages 114-139, February 2004.
J1 Prabhat Mishra, Nikil Dutt, and Hiroyuki Tomiyama, Towards Automatic Validation of Dynamic Behavior in Pipelined Processor Specifications, Kluwer Design Automation for Embedded Systems (DAES), volume 8, number 2, pages 249-265, 2003.

Patents

P2 Prabhat Mishra, Seok-Won Seong, Kanad Basu, Weixun Wang, Xiaoke Qin, Chetan Murthy, Lossless Data Compression and Real-time Decompression, USPTO Patent Application 20100223237, 2010.
P1 Prabhat Mishra and Nikil Dutt, Functional Coverage driven Test Generation for Validation of Pipelined Processors, US Patent 7533294, May 12, 2009.

Book Chapters

BC17 Farimah Farahmandi, Yuanwen Huang and Prabhat Mishra, Formal Approaches to Hardware Trust Verification, The Hardware Trojan War: Attacks, Myths, and Defenses, S. Bhunia and M. Tehranipoor (editors), Springer, 2017.
BC16 Prabhat Mishra, Mark Tehranipoor and Swarup Bhunia, Security and Trust Vulnerabilities in Third-party IPs, Hardware IP Security and Trust, P. Mishra, S. Bhunia and M. Tehranipoor (editors), Springer, 2017.
BC15 Prabhat Mishra, Swarup Bhunia and Mark Tehranipoor, The Future of Trustworthy SoC Design, Hardware IP Security and Trust, P. Mishra, S. Bhunia and M. Tehranipoor (editors), Springer, 2017.
BC14 Yuanwen Huang and Prabhat Mishra, Test Generation for Detection of Malicious Parametric Variations, Hardware IP Security and Trust, P. Mishra, S. Bhunia and M. Tehranipoor (editors), Springer, 2017.
BC13 Farimah Farahmandi and Prabhat Mishra, Validation of IP Security and Trust, Hardware IP Security and Trust, P. Mishra, S. Bhunia and M. Tehranipoor (editors), Springer, 2017.
BC12 Anupam Chattopadhyay, Nikil Dutt, Rainer Leupers and Prabhat Mishra, Processor Modeling and Design Tools, Electronic Design Automation for Integrated Circuits Handbook (Second Edition), L. Lavagno, I. Markov, G. Martin and L. Scheffer (Editors), CRC Press, 2016.
BC11 Sandip Ray, Swarup Bhunia and Prabhat Mishra, Security Validation in System-on-Chip, Fundamentals of IP and SoC Security - Design, Verification and Debug, S. Bhunia, S. Ray and S. Sur-Kolay (editors), Springer, 2016.
BC10 Prabhat Mishra, Computer Architecture, Encyclopedia of Life Support Systems (EOLSS), United Nations Educational, Scientific and Cultural Organization (UNESCO), 2012.
BC9 Weixun Wang, Xiaoke Qin and Prabhat Mishra, Energy-Aware Dynamic Cache Reconfigurations and Voltage Scaling in Real-Time Systems, Handbook of Energy-Aware and Green Computing, I. Ahmad and S. Ranka, Editors, Chapman & Hall/CRC Press, pages 543-572, 2011.
BC8 Nirmalya Bandyopadhyay, Kanad Basu and Prabhat Mishra, HMDES, ISDL and Other Contemporary ADLs, Processor Description Languages: Applications and Methodologies, Prabhat Mishra and Nikil Dutt, Editors, Morgan Kaufmann Publishers, 2008.
BC7 Prabhat Mishra and Nikil Dutt, EXPRESSION: An ADL for Software Toolkit Generation, Exploration, and Validation of Programmable SOC Architectures, Processor Description Languages: Applications and Methodologies, Prabhat Mishra and Nikil Dutt, Editors, Morgan Kaufmann Publishers, 2008.
BC6 Prabhat Mishra and Aviral Shrivastava, ADL-driven Methodologies for Design Automation of Embedded Processors, Processor Description Languages: Applications and Methodologies, Prabhat Mishra and Nikil Dutt, Editors, Morgan Kaufmann Publishers, 2008.
BC5 Prabhat Mishra and Nikil Dutt, Introduction to Architecture Descripton Languages, Processor Description Languages: Applications and Methodologies, Prabhat Mishra and Nikil Dutt, Editors, Morgan Kaufmann Publishers, 2008.
BC4 Prabhat Mishra and Nikil Dutt, Architecture Description Languages, Customizable and Configurable Embedded Processors, Paolo Ienne and Rainer Leupers, Editors, Morgan Kaufmann Publishers, 2006.
BC3 Prabhat Mishra and Nikil Dutt, Processor Modeling and Design Tools, The EDA Handbook, L. Scheffer, L. Lavagno and G. Martin (Editors), CRC Press, 2006.
BC2 Prabhat Mishra and Nikil Dutt, Architecture Description Languages for Programmable Embedded Systems, System On Chip: Next Generation Electronics, Bashir M. Al-Hashimi, Editor, IEE Press, 2005.
BC1 Prabhat Mishra and Nikil Dutt, Modeling and Verification of Pipelined Embedded Processors in the Presence of Hazards and Exceptions, in Design and Analysis of Distributed Embedded Systems, Bernd Kleinjohann et al., Editors, Kluwer Academic Publishers, 2002, pp. 81-90.

Referred Conference Papers

C80 Farimah Farahmandi and Prabhat Mishra, FSM Anomaly Detection using Formal Analysis, IEEE International Conference on Computer Design (ICCD), pages -, Boston, Massachusetts, November 5 - 8, 2017.
C79 Farimah Farahmandi and Prabhat Mishra, Automated Debugging of Arithmetic Circuits using Incremental Gröbner Basis Reduction, IEEE International Conference on Computer Design (ICCD), pages -, Boston, Massachusetts, November 5 - 8, 2017.
C78 Alif Ahmed and Prabhat Mishra, QUEBS: Qualifying Event Based Search in Concolic Testing for Validation of RTL Models, IEEE International Conference on Computer Design (ICCD), pages -, Boston, Massachusetts, November 5 - 8, 2017.
C77 Yuanwen Huang and Prabhat Mishra, Vulnerability-aware Energy Optimization using Cache Reconfiguration and Partitioning in Multicore Systems, IEEE International Conference on Computer Design (ICCD), pages -, Boston, Massachusetts, November 5 - 8, 2017.
C76 Kamran Rahmani and Prabhat Mishra, Feature-based Signal Selection for Post-silicon Debug using Machine Learning, IEEE International Conference on Computer Design (ICCD), pages -, Boston, Massachusetts, November 5 - 8, 2017.
C75 Farimah Farahmandi, Ronny Morad, Avi Ziv, Ziv Nevo and Prabhat Mishra, Cost-Effective Analysis of Post-Silicon Functional Coverage Events, Design Automation and Test in Europe (DATE), pages -, Lausanne, Switzerland, March 27 - 31, 2017.
C74 Farimah Farahmandi, Yuanwen Huang and Prabhat Mishra, Trojan Localization using Symbolic Algebra, Asia and South Pacific Design Automation Conference (ASPDAC), pages -, Tokyo, Japan, January 16 - 19, 2017. Nominated for Best Paper Award
C73 Yuanwen Huang, Swarup Bhunia and Prabhat Mishra, MERS: Statistical Test Generation for Side-Channel Analysis based Trojan Detection, ACM Conference on Computer and Communications Security (CCS), pages 130-141, Vienna, Austria, October 24 - 28, 2016.
C72 Xiaolong Guo, Raj Gautam Dutta, Prabhat Mishra and Yier Jin, Scalable SoC Trust Verification using Integrated Theorem Proving and Model Checking, IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pages 124-129, McLean, Virginia, May 3 - 5, 2016.
C71 Farimah Farahmandi and Prabhat Mishra, Automated Test Generation for Debugging Arithmetic Circuits, Design Automation and Test in Europe (DATE), pages 1351 - 1356, Dresden, Germany, March 14 - 18, 2016.
C70 Farimah Farahmandi, Prabhat Mishra and Sandip Ray, Exploiting Transaction Level Models for Observability-aware Post-silicon Test Generation, Design Automation and Test in Europe (DATE), pages 1477-1480, Dresden, Germany, March 14 - 18, 2016.
C69 Yuanwen Huang and Prabhat Mishra, Reliability and Energy-aware Cache Reconfiguration for Embedded Systems, IEEE International Symposium on Quality Electronic Design (ISQED), pages 313-318, Santa Clara, California, March 15-16, 2016. Best Paper Award
C68 Sudhi Proch and Prabhat Mishra, Test Generation for Hybrid Systems using Clustering and Learning Techniques, International Conference on VLSI Design, pages 589-590, Kolkata, India, January 4-8, 2016.
C67 Yuanwen Huang, Anupam Chattopadhyay and Prabhat Mishra, Trace Buffer Attack: Security versus Observability Study in Post-Silicon Debug, IEEE International Conference on Very Large Scale Integration (VLSI-SoC), pages 355-360, Daejeon, Korea, October 5-7, 2015.
C66 Xiaolong Guo, Raj Gautam Dutta, Yier Jin, Farimah Farahmandi and Prabhat Mishra, Pre-Silicon Security Verification and Validation: A Formal Perspective, ACM/IEEE Design Automation Conference (DAC), pages 145:1-145:6, 2015.
C65 Zhe Wang, Sanjay Ranka and Prabhat Mishra, Efficient Task Partitioning and Scheduling for Thermal Management in Multicore Processors, IEEE International Symposium on Quality Electronic Design (ISQED), pages -, Santa Clara, California, March 2-4, 2015.
C64 Mingsong Chen, Daian Yue, Xiaoke Qin, Xin Fu and Prabhat Mishra, Variation-Aware Evaluation of MPSoC Task Allocation and Scheduling Strategies using Statistical Model Checking, Design Automation and Test in Europe (DATE), pages 199 - 204, Grenoble, France, March 9 - 13, 2015.
C63 Hadi Hajimiri, Kamran Rahmani and Prabhat Mishra, Efficient Peak Power Estimation using Probabilistic Cost-Benefit Analysis, International Conference on VLSI Design, pages 369-374, Bengaluru, India, January 3-7, 2015.
C62 Prateek Thakyal and Prabhat Mishra, Layout-aware Selection of Trace Signals for Post-Silicon Debug, IEEE International Symposium on VLSI (ISVLSI), pages 326-331, 2014.
C61 Prateek Thakyal and Prabhat Mishra, Layout-aware Signal Selection for Reconfigurable Architectures, International Symposium on VLSI Design and Test (VDAT), pages 1-6, 2014.
C60 Sudhi Proch and Prabhat Mishra, Directed Test Generation for Hybrid Systems, IEEE International Symposium on Quality Electronic Design (ISQED), pages 156-162, Santa Clara, California, March 10-12, 2014.
C59 Kamran Rahmani, Prabhat Mishra and Sandip Ray, Efficient Trace Signal Selection using Augmentation and ILP Techniques, IEEE International Symposium on Quality Electronic Design (ISQED), pages 148-155, Santa Clara, California, March 10-12, 2014.
C58 Xiaoke Qin and Prabhat Mishra, TECS: Temperature- and Energy-Constrained Scheduling for Multicore Systems, International Conference on VLSI Design, pages 216-221, Mumbai, India, January 7-9, 2014.
C57 Xiaoke Qin and Prabhat Mishra, Scalable Test Generation by Interleaving Concrete and Symbolic Execution, International Conference on VLSI Design, pages 104-109, Mumbai, India, January 7-9, 2014.
C56 Kamran Rahmani, Prabhat Mishra and Sandip Ray, Scalable Trace Signal Selection using Machine Learning, IEEE International Conference on Computer Design (ICCD), pages 384-389, Asheville, North Carolina, October 6-9, 2013.
C55 Hadi Hajimiri, Mimonah Al Qathrady and Prabhat Mishra, Proactive Thermal Management Using Memory Based Computing, IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH), pages 110-115, New York, July 15-17, 2013. Nominated for Best Paper Award
C54 Hadi Hajimiri, Prabhat Mishra, Swarup Bhunia, Branden Long, Yibo Li and Rashmi Jha, Content-aware Encoding for Improving Energy Efficiency in Multi-Level Cell Resistive Random Access Memory, IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH), pages 76-81, New York, July 15-17, 2013.
C53 Mingsong Chen, Saijie Huang, Geguang Pu and Prabhat Mishra, Branch-and-Bound Style Resource Constrained Scheduling using Efficient Structure-Aware Pruning, IEEE International Symposium on VLSI (ISVLSI), pages 224-229, Natal, Brazil, August 5-7, 2013.
C52 Mingsong Chen and Prabhat Mishra, Assertion-Based Functional Consistency Checking between TLM and RTL Models, International Conference on VLSI Design, pages 320-325, Pune, India, January 5-10, 2013. Nominated for Best Paper Award
C51 Kanad Basu, Prabhat Mishra and Priyadarsan Patra, Observability-aware Directed Test Generation for Soft Errors and Crosstalk Faults, International Conference on VLSI Design, pages 291-296, Pune, India, January 5-10, 2013.
C50 Kamran Rahmani and Prabhat Mishra, Efficient Signal Selection using Fine-grained Combination of Scan and Trace Buffers, International Conference on VLSI Design, pages 308-313, Pune, India, January 5-10, 2013.
C49 Hadi Hajimiri, Prabhat Mishra and Swarup Bhunia, Dynamic Cache Tuning for Efficient Memory Based Computing in Multicore Architectures, International Conference on VLSI Design, pages 49-54, Pune, India, January 5-10, 2013.
C48 Kamran Rahmani, Hadi Hajimiri, Kartik Shrivastava and Prabhat Mishra, Synergistic Integration of Code Encryption and Compression in Embedded Systems, ACM Great Lakes Symposium on VLSI (GLSVLSI), pages 363- 368, Salt Lake City, USA, May 3-4, 2012.
C47 Kamran Rahmani, Prabhat Mishra and Swarup Bhunia, Memory-based Computing for Performance and Energy Improvement in Multicore Architectures, ACM Great Lakes Symposium on VLSI (GLSVLSI), pages 287-290, Salt Lake City, USA, May 3-4, 2012.
C46 Xiaoke Qin and Prabhat Mishra, Automated Generation of Directed Tests for Transition Coverage in Cache Coherence Protocols, Design Automation and Test in Europe (DATE), pages 3-8, Dresden, Germany, March 12 - 16, 2012. Nominated for Best Paper Award
C45 Hadi Hajimiri and Prabhat Mishra, Intra-task Dynamic Cache Reconfiguration, International Conference on VLSI Design, pages 430-435, Hyderabad, India, January 9-11, 2012.
C44 Zhe Wang, Sanjay Ranka and Prabhat Mishra, Temperature-aware Task Partitioning for Real-Time Scheduling in Embedded Systems, International Conference on VLSI Design, pages 161-166, Hyderabad, India, January 9-11, 2012.
C43 Kanad Basu, Prabhat Mishra and Priyadarsan Patra, Efficient Combination of Trace and Scan Signals for Post Silicon Validation and Debug, IEEE International Test Conference (ITC), pages 1-8 , Anaheim, California, USA, September 18-23, 2011.
C42 Weixun Wang, Prabhat Mishra and Sanjay Ranka, Dynamic Cache Reconfiguration and Partitioning for Energy Optimization in Real-Time Multi-Core Systems, ACM/IEEE Design Automation Conference (DAC), pages 948-953, 2011.
C41 Hadi Hajimiri, Kamran Rahmani, and Prabhat Mishra, Synergistic Integration of Dynamic Cache Reconfiguration and Code Compression in Embedded Systems, International Green Computing Conference (IGCC), pages 1-8, Orlando, Florida, July 25-28, 2011.
C40 Hadi Hajimiri, Somnath Paul, Anandaroop Ghosh, Swarup Bhunia and Prabhat Mishra, Reliability Improvement in Multicore Architectures Through Computing in Embedded Memory, IEEE International Midwest Symposium on Circuits and Systems (MWSCAS), pages , Seoul, Korea, August 7-10, 2011.
C39 Xiaoke Qin and Prabhat Mishra, Efficient Directed Test Generation for Validation of Multicore Architectures, International Symposium on Quality Electronic Design (ISQED), pages 276-283, Santa Clara, California, March 14-16, 2011.
C38 Kanad Basu and Prabhat Mishra, Efficient Trace Data Compression using Statically Selected Dictionary, IEEE VLSI Test Symposium (VTS), pages 14-19, Dana Point, California, May 1-5, 2011.
C37 Mingsong Chen and Prabhat Mishra, Decision Ordering Based Property Decomposition for Functional Test Generation, Design Automation and Test in Europe (DATE), pages 167-172, Grenoble, France, March 14 - 18, 2011.
C36 Kanad Basu and Prabhat Mishra, Efficient Trace Signal Selection for Post Silicon Validation and Debug, International Conference on VLSI Design, pages 352-357, Chennai, India, January 2-7, 2011. Best Paper Award
C35 Kartik Shrivastava and Prabhat Mishra, Dual Code Compression for Embedded Systems, International Conference on VLSI Design, pages 177-182, Chennai, India, January 2-7, 2011.
C34 Weixun Wang, Sanjay Ranka and Prabhat Mishra, A General Algorithm for Energy-Aware Dynamic Reconfiguration in Multitasking Systems, International Conference on VLSI Design, pages 334-339, Chennai, India, January 2-7, 2011.
C33 Weixun Wang and Prabhat Mishra, Pre-DVS: Preemptive Dynamic Voltage Scaling for Real-Time Systems with Approximation Scheme, ACM/IEEE Design Automation Conference (DAC), pages 705 - 710, Anaheim, California, USA, June 13-18, 2010.
C32 Weixun Wang, Xiaoke Qin and Prabhat Mishra, Temperature- and Energy-Constrained Scheduling in Multitasking Systems: A Model Checking Approach, ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED), pages 85 - 90, Austin, Texas, USA, August 18-20, 2010.
C31 Mingsong Chen, Xiaoke Qin and Prabhat Mishra, Efficient Decision Ordering Techniques for SAT-based Test Generation, Design Automation and Test in Europe (DATE), pages 490-495, Dresden, Germany, March 8 - 12, 2010.
C30 Xiaoke Qin, Mingsong Chen and Prabhat Mishra, Synchronized Generation of Directed Tests using Satisfiability Solving, International Conference on VLSI Design, pages 351-356, Bangalore, India, January 3-7, 2010.
C29 Weixun Wang and Prabhat Mishra, Leakage-Aware Energy Minimization using Dynamic Voltage Scaling and Cache Reconfiguration in Real-Time Systems, International Conference on VLSI Design, pages 357-362, Bangalore, India, January 3-7, 2010.
C28 Nga Dang, Abhik Roychoudhury, Tulika Mitra and Prabhat Mishra, Generating Test Programs to Cover Pipeline Interactions, ACM/IEEE Design Automation Conference (DAC), pages 142-147, San Francisco, California, USA, July 26-31, 2009. Nominated for Best Paper Award
C27 Weixun Wang and Prabhat Mishra, Dynamic Reconfiguration of Two-Level Caches in Soft Real-Time Embedded Systems, IEEE International Symposium on VLSI (ISVLSI), pages 145-150, Tampa, Florida, USA, May 13-15, 2009.
C26 Chetan Murthy and Prabhat Mishra, Lossless Compression using Efficient Encoding of Bitmasks, IEEE International Symposium on VLSI (ISVLSI), pages 163-168, Tampa, Florida, USA, May 13-15, 2009.
C25 Chetan Murthy and Prabhat Mishra, Bitmask-based Control Word Compression for NISC Architectures, ACM Great Lakes Symposium on VLSI (GLSVLSI), pages 321-326, Boston, USA, May 10-12, 2009.
C24 Xiaoke Qin and Prabhat Mishra, Efficient Placement of Compressed Code for Parallel Decompression, International Conference on VLSI Design, pages 335-340, New Delhi, India, January 5-9, 2009.
C23 Weixun Wang, Prabhat Mishra and Ann-Gordon Ross, SACR: Scheduling-Aware Cache Reconfiguration for Real-Time Embedded Systems, International Conference on VLSI Design, pages 547-552, New Delhi, India, January 5-9, 2009.
C22 Prabhat Mishra and Mingsong Chen, Efficient Techniques for Directed Test Generation using Incremental Satisfiability, International Conference on VLSI Design, pages 65-70, New Delhi, India, January 5-9, 2009. Nominated for Best Paper Award
C21 Heon-Mo Koo and Prabhat Mishra, Specification-based Compaction of Directed Tests for Functional Validation of Pipelined Processors, International Symposium on Hardware/Software Codesign and System Synthesis (CODES+ISSS), pages 137-142, Atlanta, USA, October 19 - 24, 2008.
C20 Kanad Basu and Prabhat Mishra, A Novel Test-Data Compression Technique using Application-Aware Bitmask and Dictionary Selection Methods, ACM Great Lakes Symposium on VLSI (GLSVLSI), pages 83-88, Orlando, USA, May 4 - 6, 2008.
C19 Mingsong Chen, Prabhat Mishra and Dhrubajyoti Kalita, Coverage-driven Automatic Test Generation for UML Activity Diagrams, ACM Great Lakes Symposium on VLSI (GLSVLSI), pages 139-142, Orlando, USA, May 4 - 6, 2008.
C18 Seok-Won Seong and Prabhat Mishra, An Efficient Code Compression Technique using Application-Aware Bitmask and Dictionary Selection Methods, Design Automation and Test in Europe (DATE), pages 582-587, Nice, France, April 16 - 20, 2007.
C17 Heon-Mo Koo and Prabhat Mishra, Automated Micro-architectural Test Generation for Validation of Modern Processors, US-Korea Conference on Global Challenges in Science and Technology (UKC), Washington DC, August 9-12, 2007.
C16 Xianfeng Li, Abhik Roychoudhury, Tulika Mitra, Prabhat Mishra and Xu Cheng, A Retargetable Software Timing Analyzer Using Architecture Description Language, Asia and South Pacific Design Automation Conference (ASPDAC), pages 396-401, Yokohama, Japan, January 23 - 26, 2007.
C15 Seok-Won Seong and Prabhat Mishra, A Bitmask-based Code Compression Technique for Embedded Systems, IEEE/ACM International Conference on Computer Aided Design (ICCAD), pages 251-254, San Jose, California, November 5 - 9, 2006.
C14 Heon-Mo Koo and Prabhat Mishra, Test Generation using SAT-based Bounded Model Checking for Validation of Pipelined Processor, ACM Great Lakes Symposium on VLSI (GLSVLSI), pages 362-365, Philadelphia, USA, April 30 - May 2, 2006.
C13 Heon-Mo Koo and Prabhat Mishra, Functional Test Generation using Property Decompositions for Validation of Pipelined Processors, Design Automation and Test in Europe (DATE), pages 1240-1245, Munich, Germany, March 6-10, 2006.
C12 Heon-Mo Koo and Prabhat Mishra, Coverage-driven Functional Test Generation for Processor Validation using Formal Methods, US-Korea Conference on Science, Technology, and Entrepreneurship (UKC), New Jersey, August 10-13, 2006.
C11 Mehrdad Reshadi and Prabhat Mishra, Memory Access Optimizations in Instruction-Set Simulators, International Symposium on Hardware/Software Codesign and System Synthesis (CODES+ISSS), pages 237-242, New York, September 19-21, 2005.
C10 Prabhat Mishra and Nikil Dutt, Functional Coverage Driven Test Generation for Validation of Pipelined Processors, Design Automation and Test in Europe (DATE), pages 678-683, Munich, Germany, March 7-11, 2005.
C9 Prabhat Mishra and Nikil Dutt, Functional Validation of Programmable Architectures, EUROMICRO Symposium on Digital System Design (DSD), pages 12-19, Rennes, France, August 31 - September 3, 2004. Keynote Paper
C8 Prabhat Mishra and Nikil Dutt, Graph-based Functional Test Program Generation for Pipelined Processors, Design Automation and Test in Europe (DATE), pages 182-187, Paris, France, February 16-20, 2004.
C7 Prabhat Mishra, Arun Kejariwal, and Nikil Dutt, Synthesis-driven Exploration of Pipelined Embedded Processors, International Conference on VLSI Design, pages 921-926, Mumbai, India, January 5-9, 2004.
C6 Mehrdad Reshadi, Nikhil Bansal, Prabhat Mishra, and Nikil Dutt, An Efficient Retargetable Framework for Instruction-Set Simulation, International Symposium on Hardware/Software Codesign and System Synthesis (CODES+ISSS), pages 13-18, California, USA, October 1-3, 2003. Best Paper Award
C5 Mehrdad Reshadi, Prabhat Mishra, and Nikil Dutt, Instruction Set Compiled Simulation: A Technique for Fast and Flexible Instruction Set Simulation, Design Automation Conference (DAC), pages 758-763, Anaheim, USA, June 2-6, 2003.
C4 Prabhat Mishra, Hiroyuki Tomiyama, Nikil Dutt, and Alex Nicolau, Automatic Verification of In-Order Execution in Microprocessors with Fragmented Pipelines and Multicycle Functional Units, Design Automation and Test in Europe (DATE), pages 36-43, Paris, France, March 4-8, 2002.
C3 Prabhat Mishra, Hiroyuki Tomiyama, Ashok Halambi, Peter Grun, Nikil Dutt, and Alex Nicolau, Automatic Modeling and Validation of Pipeline Specifications driven by an Architecture Description Language, Asia and South Pacific Design Automation Conference (ASPDAC) & VLSI Design, pages 458-463, Bangalore, India, January 7-11, 2002.
C2 Prabhat Mishra, Nikil Dutt, and Alex Nicolau, Functional Abstraction driven Design Space Exploration of Heterogeneous Programmable Architectures, International Symposium on System Synthesis (ISSS), Montreal, Canada, October 1-3, pages 256-261, 2001.
C1 Prabhat Mishra, Peter Grun, Nikil Dutt, and Alex Nicolau, Processor-Memory Co-Exploration driven by a Memory-Aware Architecture Description Language, International Conference on VLSI Design, pages 70-75, Bangalore, India, January 3-7, 2001.

Premier Referred Workshop Papers

W13 X. Guo, R. Dutta, P. Mishra and Y. Jin, Automatic RTL-to-Formal Code Converter for IP Security Formal Verification, IEEE International Workshop on Microprocessor Test and Verification (MTV), pages , Austin, Texas, December 12-13, 2016.
W12 Kanad Basu, Prabhat Mishra, Priyadarsan Patra, Amir Nahir and Allon Adir, Dynamic Selection of Trace Signals for Post-Silicon Debug, IEEE International Workshop on Microprocessor Test and Verification(MTV), pages 62-67, Austin, Texas, December 11-13, 2013.
W11 Kanad Basu, Prabhat Mishra and Priyadarsan Patra, Constrained Signal Selection for Post-Silicon Validation, IEEE International High Level Design Validation and Test Workshop (HLDVT), pages 71-75, Huntington Beach, California, November 9-10, 2012.
W10 Mingsong Chen, Prabhat Mishra and Dhrubajyoti Kalita, Towards RTL Test Generation from SystemC TLM Specifications, IEEE International High Level Design Validation and Test Workshop (HLDVT), pages 91-96, Irvine, California, November 7-9, 2007.
W9 Heon-Mo Koo, Prabhat Mishra, Jayanta Bhadra and Magdy Abadir, Directed Micro-architectural Test Generation for an Industrial Processor: A Case Study, IEEE International Workshop on Microprocessor Test and Verification (MTV), pages 33-36, Austin, Texas, USA, December 4-5, 2006.
W8 Prabhat Mishra, Heon-Mo Koo, and Zhuo Huang, Language-driven Validation of Pipelined Processors using Satisfiability Solvers, IEEE International Workshop on Microprocessor Test and Verification (MTV), pages 119-126, Austin, Texas, USA, November 3-4, 2005.
W7 Prabhat Mishra, Nikil Dutt, and Yaron Kashai, Functional Verification of Pipelined Processors: A Case Study, IEEE International Workshop on Microprocessor Test and Verification (MTV), pages 79-84, Austin, USA, September 9-10, 2004.
W6 Prabhat Mishra, Arun Kejariwal and Nikil Dutt, Rapid Exploration of Pipelined Processors through Automatic Generation of Synthesizable RTL Models, IEEE International Workshop on Rapid System Prototyping (RSP), pages 226-232, San Diego, USA, June 9-11, 2003.
W5 Prabhat Mishra and Nikil Dutt, A Methodology for Validation of Microprocessors using Equivalence Checking, IEEE International Workshop on Microprocessor Test and Verification (MTV), pages 83-88, Austin, USA, May 29-30, 2003.
W4 Prabhat Mishra and Nikil Dutt, Automatic Functional Test Program Generation for Pipelined Processors using Model Checking, IEEE International High Level Design Validation and Test Workshop (HLDVT), pages 99-103, Cannes, France, October 27-29, 2002.
W3 Prabhat Mishra, Narayanan Krishnamurthy, Nikil Dutt and Magdy Abadir, A Property Checking Approach to Microprocessor Verification using Symbolic Simulation, Microprocessor Test and Verification (MTV), Austin, Texas, June 6-7, 2002.
W2 Prabhat Mishra, Nikil Dutt, and Alex Nicolau, Automatic Validation of Pipeline Specifications, IEEE International High Level Design Validation and Test Workshop (HLDVT), pages 9-13, Monterey, California, November 7-9, 2001.
W1 Prabhat Mishra, Frederic Rousseau, Nikil Dutt, and Alex Nicolau, Architecture Description Language driven Design Space Exploration in the Presence of Coprocessors, Synthesis And System Integration of MIxed Technologies (SASIMI), Nara, Japan, October 18-19, 2001.

Keynotes

K1 Prabhat Mishra, Cruising the Landscape of System Validation: Dangers and Opportunities, International Symposium on VLSI Design and Test (VDAT), Coimbatore, July 18, 2014.

Panels

P1 Prabhat Mishra, Sharad Kumar (Freescale), Eric Rentschler (Mentor Graphics), Kevin Reick (IBM), Daniel Sorin ( Duke Univ.), Diagnosing Disaster: Getting to Post-Silicon, ACM/IEEE Design Automation Conference (DAC), San Francisco, June 5, 2014.

Tutorials

T3 Sharad Kumar (NXP), John Schumann (IBM), Sukhbinder Singh (Intel), Sankaran Menon (Intel), and Prabhat Mishra, The Future of SoC System Validation & Debug. and Why You Should Care!, Design Automation Conference (DAC), Austin, Texas, June 19, 2017.
T2 Prabhat Mishra, Swarup Bhunia (Case Western Reserve University), and Srivaths Ravi (Texas Instruments), Validation and Debug of Security and Trust Issues in Embedded Systems, International Conference on VLSI Design, Bangalore, India, January 4, 2015.
T1 Prabhat Mishra, Masahiro Fujita (Univ. of Tokyo), Virendra Singh (IIT Bombay), Nagesh Tamarapalli (AMD), Sharad Kumar (Freescale) and Rajesh Mittal (TI), Post-Silicon Validation, Debug and Diagnosis, International Conference on VLSI Design, Pune, India, January 6, 2013.

Non-Referred Publications (Guest Editorials, Special Sessions, ...)

M8 Prabhat Mishra, Towards Trust Validation of Hardware Intellectual Property (IP) Cores, Special session on New Directions in Hardware Security, International Conference on VLSI Design, Kolkata, India, January 4-8, 2016.
M7 Zeljko Zilic, Prabhat Mishra and Sandeep Shukla, Guest Editors' Introduction: Special Section on System-Level Design and Validation of Heterogeneous Chip Multiprocessors, IEEE Transactions on Computers, 62(2), pages 209-210, February 2013.
M6 Prabhat Mishra, Zeljko Zilic and Sandeep Shukla, Guest Editors' Introduction: Multicore SoC Validation with Transaction-Level Models, IEEE Design & Test of Computers, 28(3), pages 6-9, May-June 2011.
M5 Sandeep Shukla, Prabhat Mishra and Zeljko Zilic, A Brief History of Multiprocessors and EDA, IEEE Design & Test of Computers, 28(3), pages 52-53, May-June 2011.
M4 Zeljko Zilic, Prabhat Mishra and Sandeep Shukla, Challenges of Rapidly Emerging Consumer Space Multiprocessors, IEEE Design & Test of Computers, 28(3), pages 52-53, May-June 2011.
M3 Prabhat Mishra, Guest Editorial, Journal of Electronic Testing, volume 26, number 2, pages 149-150, 2010.
M2 Prabhat Mishra, Guest Editor Introduction: Special Issue on Nano/Bio-Inspired Applications and Architectures, International Journal of Parallel Programming, volume 37, number 4, pages 343-344, 2009.
M1 Prabhat Mishra, Processor Validation: A Top-Down Approach, IEEE Potentials, February/March 2005.