Post-Silicon Validation and Debug

Overview

Post-Silicon Validation and Debug are extremely important in modern IC design process. With increase in design complexity and decrease in time-to-market window, many of the bugs escape the pre-silicon phase. It is necessary to locate and fix these bugs before a chip is delivered to the customer. Recent studies reveal that at 65nm, the industry spends around half of the expenses in post-silicon debug.

The primary problem of post-silicon validation is the limited observability of internal signals. Since a chip has already been manufactured, it is not possible to observe each and every internal signal states. Recent DfD techniques like Embedded Logic Analyzer (ELA) allows us to store some of the selected signal states in an on-chip trace buffer. The data from the trace buffer is then dumped to an offline debugger for debugging. Limited trace buffer size constraints the number of signals to be selected for tracing. Therefore, the signals to be traced should be carefully selected so that a maximum restoration of the untraced signals is obtained. Existing signal selection approaches used partial restorability based signal selection which neither provided a high restoration ratio, nor were computationally efficient. We have developed a total restorability based signal selection algorithm which can provide up to 3 times higher restoration compared to the existing approaches and reduce the signal selection time by 90%.

To further increase the observation window, we can compress the debug traces. We have proposed a static dictionary based compression algorithm that can provide up to 84% better compression than the existing dynamic dictionary based compression approaches while reducing the hardware overhead by 60%. Further, we have explored how to combine trace and scan data in order to obtain a higher restoration. Our approach is seen to provide a 17% improvement over existing trace-scan combinations.

Members


   Faculty (PI)    Graduate Students
   Prof. Prabhat Mishra    Kanad Basu

Publications


Journal Articles:
J1 Kanad Basu and Prabhat Mishra, Test Data Compression using Efficient Bitmask and Dictionary Selection Methods, IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI), volume 18, issue 9, pages 1277-1286, 2010. DOI: 10.1109/TVLSI.2009.2024116

Referred Conference Papers:
C4 Kanad Basu, Prabhat Mishra and Priyadarsan Patra, Efficient Combination of Trace and Scan Signals for Post Silicon Validation and Debug, IEEE International Test Conference (ITC), pages - , Anaheim, California, USA, September 18-23, 2011.
C3 Kanad Basu and Prabhat Mishra, Efficient Trace Data Compression using Statically Selected Dictionary, Accepted to appear in IEEE VLSI Test Symposium (VTS), pages -, Dana Point, California, May 1-5, 2011.
C2 Kanad Basu and Prabhat Mishra, Efficient Trace Signal Selection for Post Silicon Validation and Debug, International Conference on VLSI Design, pages -, Chennai, India, January 2-7, 2011. Best Paper Award
C1 Kanad Basu and Prabhat Mishra, A Novel Test-Data Compression Technique using Application-Aware Bitmask and Dictionary Selection Methods, ACM Great Lakes Symposium on VLSI (GLSVLSI), pages 83-88, Orlando, USA, May 4 - 6, 2008.

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Research Sponsors

National Science Foundation This project is funded by the National Science Foundation (NSF). The views expressed on the site are those of the members of this project and do not necessarily represent those of the National Science Foundation.
Intel Corporation This project is funded by the Intel Corporation. The views expressed on the site are those of the members of this project and do not necessarily represent those of the Intel.