Post-Silicon Validation and Debug

Post-silicon validation is widely acknowledged as a major bottleneck for complex integrated circuits (ICs) including modern microprocessors as well as complex System-on-Chip (SoC) designs. Recent studies suggest that post-silicon validation consumes more than 50% of an SoC's overall design effort (total cost) at 65nm technology. This problem is expected to get worse as the industry continues to move to even smaller geometries. Due to increasing design complexity coupled with shrinking time-to-market constraints, it is not possible to detect all design flaws (errors) during pre-silicon validation. Post-silicon validation needs to capture these escaped functional errors as well as electrical faults including crosstalk, delay and transient faults.

This book will be a comprehensive reference for SoC designers, validation engineers as well as researchers interested in post-silicon validation and debug of heterogeneous SoCs. This book will include contributions from experts in the field post-silicon validation and debug both from industry and academia. The book will cover a wide variety of state-of-the-art SoC debug infrastructure, post-silicon validation methods, and post-fabrication debug techniques.

   Part I: Introduction
        Post-Silicon SoC Validation ChallengesFarimah Farahmandi and Prof. Prabhat Mishra, University of Florida
   Part II: Debug Infrastructure
        On-chip InstrumentationDr. Sandip Ray, University of Florida
        Metric-based Signal SelectionDr. Kanad Basu, New York University
        Simulation-based Signal SelectionDr. Debapriya Chatterjee (IBM) and Prof. Valeria Bertacco (University of Michigan)
        Hybrid Signal SelectionDr. Azadeh Davoodi, University of Wisconsin
        Post-Silicon Signal Selection using Machine LearningAlif Ahmed, Dr. Kamran Rahmani and Prof. Prabhat Mishra, University of Florida
   Part III: Generation of Tests and Assertions
        Observability-aware Post-Silicon Test GenerationFarimah Farahmandi and Prof. Prabhat Mishra, University of Florida
        On-chip Constrained-Random Stimuli GenerationDr. Xiaobing Shi and Prof. Nicola Nicolici, McMaster University
        Test Generation and Lightweight Checking for Multi-core Memory Consistency Doowon Lee and Prof. Valeria Bertacco (University of Michigan)
        Selection of Post-Silicon Hardware AssertionsDr. Pouya Taatizadeh and Prof. Nicola Nicolici, McMaster University
   Part IV: Post-Silicon Debug
        Debug Data Reduction TechniquesDr. Sandeep Chandran and Prof. Preeti Ranjan Panda, Indian Institute of Technology, Delhi
        High-level Debug of Post-silicon FailuresProf. Masahiro Fujita, Qinhao Wang and Yusuke Kimura, University of Tokyo
        Post-silicon Fault-localization with Satisfiability SolversProf. Georg Weissenbacher, TU Wien and Prof. Sharad Malik, Princeton
        Coverage Evaluation and Analysis of Post-silicon Tests with Virtual PrototypesDr. Kai Cong and Prof. Fei Xie, Portland State University
        Utilization of Debug Infratsructure for Post-Silicon Coverage AnalysisFarimah Farahmandi and Prof. Prabhat Mishra, University of Florida
   Part V: Case Studies
        Network-on-Chip Validation and DebugSubodha Charles and Prof. Prabhat Mishra, University of Florida
        Post-silicon Validation of the IBM Power8 ProcessorTom Kolan, Hillel Mendelson, Amir Nahir, Vitali Sokhin, IBM
   Part VI: Conclusion and Future Directions
        SoC Security versus Post-Silicon Debug ConflictYangdi Lyu, Dr. Yuanwen Huang and Prof. Prabhat Mishra, University of Florida
        The Future of Post-Silicon DebugFarimah Farahmandi and Prof. Prabhat Mishra, University of Florida